Microprocessors or controllers are used in a wide variety of applications to control the activities of a variety of devices. Such electronic devices require a power supply in order to perform their functions. Depending on the design of a particular device, the voltage applied may need to be within certain parameters to ensure proper function of the device receiving the output power. Accordingly, various methods are known for controlling an output power that is applied to electronic devices such as microprocessors, controllers, and their peripherals.
One particular type of structure that is used to provide a power or voltage to microcontrollers, controllers, and their peripherals is called a low drop-out voltage regulator (LDO). Generally speaking, low drop-out voltage regulators monitor an aspect of the power applied to an electronic device such as a microprocessor or associated peripheral and provides a feedback that allows control circuitry to maintain the power within certain parameters. An example environment in which a low drop-out voltage regulator is applied is illustrated in FIG. 1. An electronic device 100 includes powered electronic aspects 105 such as a central processing unit and associated peripherals that receive power from a battery 110. The battery in this case represents a system voltage that is available to the electronic device 100, which voltage may come from a battery or any other available power source. The LDO 115 operates in both an analog domain and a digital domain such that the LDO is able to provide an analog output power to the electronic aspects 105 while being controlled at least in part in the digital domain. For example, the LDO 115 may receive a reference current or voltage from the reference biasing supervision circuit 120, which reference current or voltage is typically provided in an analog format to the LDO 115. Moreover, the LDO is able to provide a feedback signal that can be used by a power management circuit 125 that, in turn, can control various elements of the LDO 115 that operate in a digital domain, which modifications to those elements help to control the output power that is provided to the electronic aspects 105. The clock management circuit 130 helps by providing information to the power management circuit 125 to further assist in controlling the operating parameters of the LDO 115.
FIG. 2 illustrates one example prior art approach to an LDO 115. In this illustration, the circuit elements covered by a diagonal arrow are all elements that are controlled in the digital domain, for example, through receipt of signals from a power management circuit 125. The circuit elements indicated in box 205 constitute the output stage of the LDO that provides an output power VCORE, which output power is provided to the electronic aspects 105. Control circuitry 212 of the LDO 115 uses a reference voltage VREF and a feedback voltage VFB to determine how to modify the digitally controlled elements to regulate the power output at VCORE.
One problem with such prior art low drop-out voltage regulators is the inability to keep up the power management features in the face of a sudden drop in applied voltage AVDD. In other words, the power source 110 provides an input power AVDD that may vary based on a load applied to the input power or other aspects of the operating electronic device 100. The LDO 115 monitors the effect of those changes and changes the control of the input voltage AVDD to try to maintain the output voltage VCORE within acceptable parameters. The circuitry elements, however, that are used to monitor these power aspects may not be able to react quickly enough to maintain the output voltage VCORE in the face of a sudden drop of the input voltage AVDD. For example, with reference to FIGS. 3 and 4, a typical input voltage AVDD in one application can range between 2.7 and 3.6 volts. The typical output voltage that is applied to power one or more electrical aspects (also called the load) is, in this case, a VCORE of about 1.2 volts. Should there be an overloading of the input power AVDD, the input power received by the low drop-out voltage regulator can drop, for example, from an initial voltage of between 2.7 and 3.6 volts to 2.0 volts or less. If that drop in input voltage AVDD occurs over too short of a timeframe, for example, between 10 and 400 microseconds, the circuitry of the low drop-out voltage regulator may not be able to maintain the output voltage VCORE. As illustrated in FIG. 3, in the face of this condition, VCORE may momentarily drop from 1.2 volts to 0 volts at point 306. Depending on the electronic aspects being powered through the low drop-out voltage regulator, a momentary drop of power could result in loss of data or other serious interruptions in the operation of these so powered electronics.
The cause of such a drop in output voltage VCORE can be further understood with reference to FIG. 4. More specifically, at the output stage 405 of the given low drop-out voltage regulator, a drop in the input voltage AVDD is illustrated by a first arrow 407. This drop in voltage, in turn causes the drop in voltage at the gate of a passgate transistor 410 through which current flows to the output of the low drop-out voltage regulator VCORE. The drop in voltage at the passgate transistor's 410 gate causes a drop in current that passes through the passgate transistor 410. The drop in current, in turn, causes a drop in voltage at the output voltage VCORE that is applied to the load 415. If this series of drops happens too quickly, the loop bandwidth or regulation speed of the low drop-out voltage regulator may simply not be able to keep up. For example, the reaction of the passgate transistor 410 and a feedback transistor 456, which provides a feedback signal to the low drop-out voltage regulators control circuitry, may not occur in time for the control circuitry to modify the operating parameters of other aspects of the low drop-out voltage regulator to maintain the output voltage VCORE at its given value. Moreover, certain low drop-out voltage regulators that are controlled in part via digital domain have limited combinations of peripheral and clock combinations that can be applied to react to such voltage drops.
Accordingly, a variety of modifications to these voltage providers have been attempted, each having its own set of drawbacks. In this example of FIG. 4, a comparator circuit 420 is connected to receive the output voltage VCORE from the low drop-out voltage regulator circuit 405. The comparator circuit 420 in this case includes a comparator circuit element 430 that compares the output voltage VCORE to a reference voltage VREF and outputs corresponding comparison signal indicated as VCORE_OK. This direct voltage monitoring approach can be made very accurate; however, this approach consumes an excess amount of additional current, thereby increasing the overall power usage of the circuit. Also, the addition of a voltage reference element and the comparator circuit elements causes an increase in the footprint of the circuit elements in the silicon. Moreover, depending on the voltage range to be measured, additional reference voltage or resistor divider circuitry elements must be added, thereby adding additional power consumption. Although this method of detecting the output voltage VCORE is accurate, by operating in a voltage domain, this approach is slower than various current mode detection approaches consuming the same or less amount of current.
Another prior art approach to controlling a low drop-out voltage regulator is illustrated in FIG. 5. Here, an example current mode monitoring approach where a sensing circuit 520 is connected to sense a current ILOAD that flows through a transistor 522 connected in parallel with the passgate transistor 510 through which the primary load current ILOAD passes. A current source 524 provides a reference current IREF for comparison to the current passing through the parallel transistor 522 by a comparator circuit element 530, such as a Schmidt Trigger Circuit Element as known in the art. Unfortunately, this approach illustrated in FIG. 5 suffers from the disadvantage that an overload event can occur that drops the input voltage AVDD and thus the output voltage VCORE below an acceptable level while the measured current stays within a valid range. In other words, the sensing approach can fail in situations where the voltage drop occurs too quickly relative to the measured current, such that this approach may not reliably detect the overload state caused by supply drops.
A further prior art approach to monitoring and controlling the output voltage from a low drop-out voltage regulator is illustrated in FIG. 6. In this approach, the current mirror circuitry 620 is connected to monitor current at a variety of points within the output stage 605 of the low drop-out voltage regulator circuit. Again, the primary current sensing is done with relation to the sensing transistor 622 that is connected in parallel to the passgate transistor 610. Accordingly, this design suffers a similar disadvantage as that of the approach of FIG. 5 where an unacceptable delay between the current drop and sensing the current drop can occur. Moreover, most low drop-out voltage regulators use bias current adaptation within the analog domain and done in continuous time. The resistors and transistors that make up the low drop-out voltage regulator circuit are not easily adapted or controlled in the analog domain. Moreover, the dynamic range of sensing the current is limited to particular ranges and limited node voltage swings.